The present invention relates to a semiconductor integrated circuit; and, more particularly, to a delay circuit for use in a synchronous dynamic random access memory, which is capable of obtaining a fast locking time and a reduced jitter.
For achieving high speed operation in a semiconductor memory device, a synchronous dynamic access memory (SDRAM) has been developed. The SDRAM operates in synchronization with an external clock signal. The SDRAM includes a single data rate (SDR) SDRAM, a double data rate (DDR) SDRAM, and the like.
Generally, when data are output in synchronization with the external clock signal, a skew between the external clock signal and the output data occurs. In the SDRAM, a delay locked loop (DLL) can be used to compensate the skew between an external clock signal and the output data, or an external clock signal and an internal clock signal.
A digital DLL is implemented with a plurality of unit delay elements that are coupled in series. For increasing a resolution, a unit delay time should be minimized. As the unit delay time becomes smaller, however, more unit delay elements are needed. Consequently, power consumption as well as chip size is increased much more.
It is, therefore, an object of the present invention to provide a delay locked loop which is capable of obtaining a fast locking time and a reduced jitter.
In accordance with an aspect of the present invention, there is provided a delay locked loop for compensating for a skew in a synchronous dynamic random access memory, comprising: a delay model for delaying an external clock signal by the skew to generate a delayed clock signal; a signal generation means, responsive to the external clock signal and the delayed clock signal, for generating control signals; a first delay means, responsive to the control signals, for delaying the delayed control signal to generate a first delay locked clock signal, wherein the first delay means has a large unit delay; and a second delay means, responsive to the control signals, for delaying the first delay locked clock signal to generate a second delay locked clock signal, wherein the second delay means has a small unit delay.